While realizing that clock rate isn't a perfect criterion for performance, I'm nevertheless curious about how fast future 45nm and 32nm processors will likely be. Does anyone have an idea of what can be expected from such processors while operating in current processors' power envelope, i.e., GHz/watt?

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While realizing that clock rate isn't a perfect criterion for performance, I'm nevertheless curious about how fast future 45nm and 32nm processors will likely be. Does anyone have an idea of what can be expected from such processors while operating in current processors' power envelope, i.e., GHz/watt?

Good question. If you know the answer, you could probably make a killing on the stock-market.

What recent developments have shown is that the power-saving/speed-increase with the latest shrinks isn't quite as good as they were some years ago when the chips were at 350/250nm.

However, with "more space" (same die-size, smaller feature-size) you can cram more "stuff" into the chip, which may not make the ultimate (theoretical) calculation capacity any better, but the average (practical) throughput is increased.

I predict bigger caches, and more cores, rather than higher clock-speeds.

Power consumption is pretty much a compromise between clock-speed and surface area - smaller surface area means the power isn't going to dissipate quickly, because there's so little area to dissipate it through [hence bigger caches on recent 90/65nm processors].

Of course, I'm a software engineer, not a process development engineer, so my views should be taken with several handfulls of salt.

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Mats

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I predict bigger caches, and more cores, rather than higher clock-speeds.

faster clock speeds, if achievable at all, also need larger cache.

This is because of relativity and the finite speed of light.

A 1GHz cpu with no cache and zero time needed to do the calcualtions needs the ram to be within 6" (15cm) of the cpu assuming the signals go at the speed of light, c; that translates to about 4" (10cm) for real signals which tend to go at 2c/3. And measure that distance along the pcb tracks, not in a straight line!

To make sure that more time is spent processing the data than waiting for the data to arrive, in the real world cache came in at around 1/5th of that speed.

A 10GHz chip would need a massive increase in on-chip cache to be useful to avoid the cpu getting left behind.

And most of that advantage can be gained by adding the extra cache without speeding up the cpu.

Which is why I agree with Mats that is the way they are likely to go rather than speeding up the clock any further.

Notice on a modern board how the bus speeds between the different levels of cache decrease as the length of the lines increases, the fastest bus being between the cpu and the on-chip cache. This configuration can be expected just from the relativity argument, no electronics or IT knowledge required.

A 30GHz cpu - if they ever go there - would probably need two levels of cache on the chip, with the communal outer cache placed near the pins and surrounding the inner layer of cores each with their own adjacent cache. Notice that at 30GHz you just about get a signal across the die in a single clock cycle but not have time to do anything with the data, hence the need for a cache that is near even in terms of the chip layout.

So if we ever do increase the clock cycle by another factor of 10, this will be well after we have learnt how to pack many many more components onto each die. By the time we crunch a WU 10x faster we'll be doing 256 at once on the same pice of silicon.

So on further reflection, I agree even more :-)

River~~

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As each die process shrinks, the components and structures shrink, and the voltage needed has gone down. At 90nm, we've shrunk from having 30 foot stone castle walls between paths of larger processes, to having the paper thin walls you see in some Japanese establishments. There's now a large problem with current leaking (and producing nothing useful.. just heat.) Intel's first 90nm die shrink was a relative disaster - with a large increase in heat production. You were better off with the 130nm part running at the same speed.
AMD is using SOI (Silicon on Insulator) to insulate the paths from each other and cut down on the current leakage. And at each step in shrinking the die size, it becomes neccessary to use more tricks to get the power supplied to the cpu to do useful work instead of just heating the cpu up. Which is why clock speeds don't seem to be increasing very fast lately.. and the current trend is to add more cores to the cpu all running at a relaxed pace. (slow).

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